1. Field of the Invention
This invention relates to the fabrication of semiconductor devices, and more particularly to a method of providing planar or uniform or selected thickness of an insulating film across a semiconductor wafer whereby the film serves as (1) a diffusion mask, (2) a passivating film, and/or (3) support means for a conductive member.
2. Description of the Prior Art
Planar processing of semiconductor wafers as integrated circuits employs an insulating film, typically silicon dioxide as a diffusion mask; passivating film, and/or support for an electrical conductor. The insulating film is formed on the surface of a semiconductor wafer by suitable processes, e.g., thermal growth, pyrolytic, anodization and the like. Openings are formed in the film by conventional photolithographic-masking-etching processes. Impurities are diffused through the openings to convert the semiconductor wafer to a different conductivity type. The insulating film is regrown simultaneously or subsequently to the impurity diffusion. Other openings are made in the regrown film for gate insulation formation; emitter diffusions or metal contact to the diffused regions.
The growing and regrowing of the insulating film normally produces an irregular or non-planar surface across the surface of the wafer. Several problems are created by the irregular or non-planar insulating film surface. One problem is that an irregular or non-planar surface introduces resolution problems in the photolithographic-masking processes. Metallized conductors formed on the insulating film have different widths across their surface due to different photoresist development. To prevent conductors from broadening and short circuiting, extra spacing or tolerances are associated with each conductor. Tolerances take up area in the wafer which reduces the number of devices that may be formed in the wafer.
Another problem is that the different thicknesses of insulation across the wafer causes over etching during the formation of openings. In the case of field effect transistors (FET), the diffused (source/drain) regions are exposed during the gate formation. The result is the metal gate formed in the gate area extends over the diffused region which noticeably increases the gate capacitance. The electrical characteristic of the device is significantly altered by such construction.
One technique for achieving an insulating film with a more regular surface is described in an article entitled "Planox Process Smoothes Path to Greater MOS Density" by F. Morandi which is described in "Electronics," Dec. 20, 1971, pages 44-48. The Planox process employs silicon nitride and silicon dioxide in combination as an insulating film. However, the Planox process only achieves a partial planar surface (see FIG. 3, Morandi reference, supra) not an entire planar surface over the substrate or wafer. Etching and conductor broadening problems are not eliminated by the Planox process. Moreover, the Planox process introduces additional processing steps and materials, i.e., silicon nitride relative to the normal planar-silicon dioxide process. The additional processing steps introduce other reliability and cost problems.
Another film planarization technique is described in Ser. No. 375,298 filed June 29, 1973, now U.S. Pat. No. 3,804,738 assigned to the same assignee as that of the present invention. Ser. No. 375,298, however, relates to sputtered film and not thermally grown film as in the present case. Moreover, the film is only partially planarized whereas the film in the present invention is fully planarized across the substrate.
The usual prior art practice for correcting the conductor broadening is by improved mask resolution. Mask resolution is improved by employing (1) photoresist that is more responsive to light and/or (2) optical equipment that produces a greater light penetration into the photoresist. In the case of over etching, the usual prior art practice is to provide a tolerance to prevent the etch from adversely affecting the adjacent diffusion regions.
As a large scale integration incorporates more and more function into a semiconductor device, however, the area available to a circuit must be utilized more efficiently. Improving device dimensional control in both horizontal and vertical directions will achieve the objective of greater density, reliability and function in large scale integration.
An object of the present invention is a process that controls insulating film thickness across a semiconductor wafer to improve device density, yield and reliability.
Another object is a process for achieving an insulating film having a planar surface or uniform thickness entirely across a semiconductor wafer employed in the manufacture of unipolar and bipolar semiconductor devices.
Another object is a process for achieving a planar insulating film of silicon dioxide entirely across a semiconductor wafer.
One specific object is a process to prevent over etching of gate regions during the fabrication of FET devices.
Another specific object is preventing or eliminating conductor line broadening during the fabrication of semiconductor devices.